Specifications

Intel
®
Quark Core—System Management Mode (SMM) Architectures
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
132 Order Number: 329679-001US
Figure 57. Redirecting System Memory Addresses to SMRAM
The following registers are saved and restored (in reserved areas of the state save),
but are not visible to the system software programmer: CR1, CR2, and CR4, hidden
descriptor registers for CS, DS, ES, FS, GS, and SS.
If an SMI# request is issued for the purpose of powering down the processor, the
values of all reserved locations in the SMM state save must be saved to non-volatile
memory.
The following registers are not automatically saved and restored by SMI# and RSM:
DR5:0, TR7:3, and the FPU registers STn, FCS, FSW, tag word, FP instruction pointer,
FP opcode, and operand pointer.
For all SMI# requests except for suspend/resume, these registers do not have to be
saved because their contents do not change. However, during a power down
suspend/resume, a resume reset clears these registers to their default values. In this
case, the suspend SMI# handler should read these registers directly to save them and
restore them during the power up resume. Anytime the SMI# handler changes these
registers in the processor, it must also save and restore them.
Table 42. SMRAM State Save Map (Sheet 1 of 2)
Register Offset Register Writeable?
2
7FFC CR0 NO
7FF8 CR3 NO
7FF4 EFLAGS YES
7FF0 EIP YES
7FEC EDI YES
7FE8 ESI YES
7FE4 EBP YES
Notes:
1. Upper two bytes are reserved.
2. Modifying a value that is marked as not writeable results in
unpredictable behavior.
3. Words are stored in two consecutive bytes in memory with
the low-order byte at the lowest address and the high-order
byte at the high address.
SMRAM
Normal
memory
space
System memory
accesses not
redirected to
SMRAM
System memory
accesses redirected
to SMRAM
Processor accesses
to system address
space used for
loading SMRAM