Specifications

Intel

Quark Core—System Management Mode (SMM) Architectures

Intel

Quark SoC X1000 Core

Developer’s Manual October 2013

134 Order Number: 329679-001US

Auto HALT Restart. It is possible for the SMI# request to interrupt the HALT state.

The SMI# handler can tell the RSM instruction to return control to the HALT instruction

or to return control to the instruction following the HALT instruction by appropriately

setting the Auto HALT Restart slot. The default operation is to restart the HALT

instruction.

I/O Trap Restart. If the SMI# interrupt was generated on an I/O access to a

powered-down device, the SMI# handler can tell the RSM instruction to re-execute that

I/O instruction by setting the I/O Trap Restart slot.

SMBASE Relocation. The system can relocate the SMRAM by setting the SMBASE

Relocation slot in the state save area. The RSM instruction sets the SMBASE in the

processor based on the value in the SMBASE Relocation slot. The SMBASE must be 32-

Kbyte aligned.

For further details on these SMM features, see Section 8.5.

If the processor detects invalid state information, it enters the shutdown state. This

happens only in the following situations:

• The value stored in the SMBASE slot is not a 32-Kbyte aligned address.

• A reserved bit of CR4 is set to 1.

• A combination of bits in CR0 is illegal; namely, (PG=1 and PE=0) or (NW=1 and

CD=0).

In shutdown mode, the processor stops executing instructions until an NMI interrupt is

received or reset initialization is invoked. The processor generates a special bus cycle to

indicate it has entered shutdown mode.

Note: INTR and SMI# also brings the processor out of a shutdown that is encountered due to

invalid state information from SMM execution. Make sure that INTR and SMI# are not

asserted if SMM routines are written such that a shutdown occurs.

8.4 System Management Mode Programming Model

8.4.1 Entering System Management Mode

SMM is one of the major operating modes, on a level with Protected Mode, Real Mode

or Virtual-86 Mode. Figure 58 shows how the processor can enter SMM from any of the

three modes and then return.