Specifications

Intel
®
Quark Core—System Management Mode (SMM) Architectures
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
138 Order Number: 329679-001US
8.5 SMM Features
8.5.1 SMM Revision Identifier
The SMM revision identifier is used to indicate the version of SMM and the SMM
extensions supported by the processor. The SMM revision identifier is written during
SMM entry and can be examined in SMRAM space at register offset 7EFCH. The lower
word of the SMM revision identifier refers to the version of the base SMM architecture.
The upper word of the SMM revision identifier refers to the extensions available (see
Figure 59).
Figure 59. SMM Revision Identifier
Bit 16 of the SMM revision identifier is used to indicate to the SMM handler that this
processor supports the SMM I/O trap extension. If this bit is high, then the processor
supports the SMM I/O trap extension. If this bit is low, then this processor does not
support I/O trapping using the I/O trap slot mechanism (see Table 44).
Bit 17 of this slot indicates whether the processor supports relocation of the SMM jump
vector and the SMRAM base address (see Table 44).
The Intel
®
Quark SoC X1000 Core supports I/O trap restart and SMBASE relocation
features.
8.5.2 Auto Halt Restart
The Auto HALT restart slot at register offset (word location) 7F02H in SMRAM indicates
to the SMM handler that the SMI# interrupted the processor during a HALT state (bit 0
of slot 7F02H is set to 1 if the previous instruction was a HALT). If the SMI# does not
interrupt the processor in a HALT state, then the SMI# microcode sets bit 0 of the Auto
HALT Restart slot to a value of 0. If the previous instruction was a HALT, the SMM
handler can choose to either set or reset bit 0. If this bit is set to 1, the RSM microcode
execution forces the processor to re-enter the HALT state. If this bit is set to 0 when
the RSM instruction is executed, the processor continues execution starting with the
instruction just after the interrupted HALT instruction. Note that if the interrupted
instruction was not a HALT instruction (bit 0 is set to 0 in the Auto HALT restart slot
upon SMM entry), setting bit 0 to 1 causes unpredictable behavior when the RSM
Table 44. Bit Values for SMM Revision Identifier
Bits Value Comments
16 0 Processor does not support I/O trap restart
16 1 Processor supports I/O trap restart
17 0 Processor does not support SMBASE relocation
17 1 Processor supports SMBASE relocation
Intel Reserved
17 16
SMM Revision Level
I/O Trap with Restart
SMBASE Relocation
Register Offset
7EFCH