Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 139
System Management Mode (SMM) Architectures—Intel
®
Quark Core
instruction is executed (see Figure 60 and Table 45).
Figure 60. Auto HALT Restart
If the HALT instruction is restarted, the processor generates a memory access to fetch
the HALT instruction (if it is not in the internal cache) and executes a HALT bus cycle.
8.5.3 I/O Instruction Restart
The I/O instruction restart slot (register offset 7F00H in SMRAM) gives the SMM handler
the option of causing the RSM instruction to automatically re-execute the interrupted
I/O instruction. When the RSM instruction is executed, if the I/O instruction restart slot
contains the value 0FFH, then the processor automatically re-executes the I/O
instruction that the SMI# trapped. If the I/O instruction restart slot contains the value
00H when the RSM instruction is executed, then the processor does not re-execute the
I/O instruction. The processor automatically initializes the I/O instruction restart slot to
00H during SMM entry. The I/O instruction restart slot should be written only when the
processor has generated an SMI# on an I/O instruction boundary. Processor operation
is unpredictable when the I/O instruction restart slot is set when the processor is
servicing an SMI# that originated on a non-I/O instruction boundary (see Figure 61
and Table 46).
Figure 61. I/O Instruction Restart
Table 45. Bit Values for Auto HALT Restart
Value of
Bit 0 at
Entry
Value of
Bit 0 at
Exit
Comments
0 0
Returns to next instruction in interrupted
program.
0 1Unpredictable.
1 0 Returns to next instruction after HALT.
1 1 Returns to HALT state.
Intel Reserved
Register Offset
7F02H
1
0
Auto HALT
Restart
15
Register Offset
7F00H
0
I/O Instruction
Restart Slot
15