Specifications
Intel
®
Quark Core—System Management Mode (SMM) Architectures
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
140 Order Number: 329679-001US
If the system executes back-to-back SMI# requests, the second SMM handler must not
set the I/O instruction restart slot (see Section 8.6.6).
8.5.4 SMM Base Relocation
The Intel
®
Quark SoC X1000 Core provides a control register, SMBASE. The address
space used as SMRAM can be modified by changing the SMBASE register before exiting
an SMI# handler routine. SMBASE can be changed to any 32-Kbyte aligned value
(values that are not 32-Kbyte aligned cause the processor to enter the shutdown state
when executing the RSM instruction). SMBASE is set to the default value of 30000H on
RESET, but is not changed on SRESET. If the SMBASE register is changed during an
SMM handler, all subsequent SMI# requests initiate a state save at the new SMBASE
(see Figure 62).
Figure 62. SMM Base Location
The SMBASE slot in the SMM state save area is used to indicate and change the SMI#
jump vector location and the SMRAM save area. When bit 17 of the SMM revision
identifier is set, then this feature exists and the SMRAM base and jump vector are as
indicated by the SMM base slot. During the execution of the RSM instruction, the
processor reads this slot and initializes the processor to use the new SMBASE during
the next SMI#. During an SMI#, the processor performs a context save to the new
SMRAM area pointed to by the SMBASE, stores the current SMBASE in the SMM Base
slot (offset 7EF8H), and then start execution of the new jump vector based on the
current SMBASE.
The SMBASE must be a 32-Kbyte aligned, 32-bit integer that indicates a base address
for the SMRAM context save area and the SMI# jump vector. For example when the
processor first powers up, the minimum SMRAM area is from 38000H-3FFFFH. The
default SMBASE is 30000H. Hence the starting address of the jump vector is calculated
by:
SMBASE + 8000H
While the starting address for the SMRAM state save area is calculated by:
SMM Base + [8000H + 7FFFH]
Hence, when this feature is enabled, the SMRAM register map is addressed according
to the above formulas (see Figure 63).
Table 46. I/O Instruction Restart Value
Value at Entry Value at Exit Comments
00H 00H Do not restart trapped I/O instruction
00H 0FFH Restart trapped I/O instruction
Register Offset
7EF8H
0
SMM Base
31










