Specifications

Intel
®
Quark Core—System Management Mode (SMM) Architectures
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
142 Order Number: 329679-001US
If SMRAM is located in its own distinct memory space, that can be completely decoded
using only the processor address signals, it is said to be non-overlaid. In this case,
there are no new requirements for maintaining cache coherency.
Figure 64. SMRAM Location
8.6.2 Cache Flushes
Note: The implementation of Intel
®
Quark Core on Intel
®
Quark SoC X1000 does not support
second-level cache.
The processor does not unconditionally flush its cache before entering SMM (this option
is left to the system designer). If SMRAM is shadowed in a cacheable memory area that
is visible to the application or operating system, it is necessary for the system to empty
both the processor cache and any second-level cache before entering SMM. That is, if
SMRAM is in the same physical address location as the normal cacheable memory
space, then an SMM read may hit the cache, which would contain normal memory
space code/data. If the SMM memory is cacheable, the normal read cycles after SMM
may hit the cache, which may contain SMM code/data. In this case the cache should be
empty before the first memory read cycle during SMM and before the first normal cycle
after exiting SMM (see Figure 65).
SMRAM
Normal
Memory
Shadowed Region
Normal
Memory
Normal
Memory
Non-overlaid
(no need to
flush caches)
Overlaid
(caches must
be flushed)
SMRAM