Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 143
System Management Mode (SMM) Architectures—Intel
®
Quark Core
Figure 65. FLUSH# Mechanism during SMM
The FLUSH# and KEN# signals can be used to ensure cache coherency when switching
between normal and SMM modes. Cache flushing during SMM entry is accomplished by
asserting the FLUSH# pin when SMI# is driven active. Cache flushing during SMM exit
is accomplished by asserting the FLUSH# pin after the SMIACT# pin is deasserted
(within one CLK). To guarantee this behavior, the constraints on setup and hold timings
on the interaction of FLUSH# and SMIACT# as specified for a processor should be
followed.
If the SMRAM area is overlaid over normal memory and if the system designer does not
want to flush the caches upon leaving SMM, then references to the SMRAM area should
not be cached. It is the obligation of the system designer to ensure that the KEN# pin
is sampled inactive during all references to the SMRAM area. Figure 66 and Figure 67
illustrate a cached and non-cached SMM using FLUSH# and KEN#.
Figure 66. Cached SMM
A5237-01
State Resume
SMI#
SMM HandlerState Slave
InstrInstr Instr
#3#1 #2
InstrInstr
#5#4
Cache must
be empty
Cache must
be empty
Flush cache
SMIACT#
SMI#
RSM
SMI#
FLUSH#
SMIACT#
A5238-01
Normal
Cycle
State
Resume
SMM
Handler
State
Slave