Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 145
System Management Mode (SMM) Architectures—Intel
®
Quark Core
If SMRAM is overlaid with normal memory space, additional system design features are
needed to ensure that cache coherency is maintained. Table 48 lists the cache flushing
requirements for entering and exiting the SMM when the SMRAM is overlaid with
normal memory space.
If SMI# and FLUSH# are asserted together, the Write-Back Enhanced Intel
®
Quark SoC
X1000 Core guarantees that FLUSH# is recognized first, followed by the SMI#. If the
cache is configured in the write-back mode, the modified lines are written back to the
normal user space, followed by the two special cycles. The SMI# is then recognized and
the transition to SMM occurs, as shown in Figure 68.
Cache flushing during SMM exit is accomplished by asserting the FLUSH# pin after the
SMIACT# pin is deasserted (within 1 CLK). To guarantee this behavior, follow the
constraints on setup and hold timings for the interaction of FLUSH# and SMIACT# as
specified for the Write-Back Enhanced Intel
®
Quark SoC X1000 Core.
The WBINVD instruction should not be used to flush the cache when exiting SMM.
Instead, the FLUSH# pin should be asserted after the SMIACT# pin is deasserted
(within one CLK). The cache coherency requirements associated with SMM and write-
through vs. write-back caches also apply to second-level cache control designs. The
appropriate second-level cache flushing also is required upon entering and exiting the
SMM.
Note: The implementation of Intel
®
Quark Core on Intel
®
Quark SoC X1000 does not support
second-level cache.
Figure 68. Write-Back Enhanced Intel
®
Quark SoC X1000 Core Cache Flushing for
Overlaid SMRAM upon Entry and Exit of Cached SMM
Table 48. Cache Flushing (Overlaid SMRAM)
Normal Memory
Cacheable
SMRAM Cacheable
FLUSH Entering
SMM
FLUSH Exiting
SMM
No No No No
No WT No Yes
WT or WB No Yes No
WT or WB WT Yes Yes
SMI#
FLUSH#
SMIACT#
A5240-01
Normal
Cycle
State
Resume
SMM
Handler
Write-
Back
Cycles
State
Slave
RSM
Flash Cache
Cache must
be empty
Cache must
be empty