Specifications

Intel
®
Quark Core—Hardware Interface
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
152 Order Number: 329679-001US
indicated by the byte enable and bus size signals. It is valid only in the clock
immediately after read data is returned to the Intel
®
Quark SoC X1000 Core. At all
other times, it is inactive (high). PCHK# is never floated.
Driving PCHK# is the only effect that bad input parity has on the Intel
®
Quark SoC
X1000 Core. The Intel
®
Quark SoC X1000 Core does not vector to a bus error interrupt
when bad data parity is returned. In systems that do not employ parity, PCHK# can be
ignored. In systems not using parity, DP[3:0] should be connected to V
CC
through a
pull-up resistor.
9.2.5 Bus Cycle Definition
9.2.5.1 M/IO#, D/C#, W/R# Outputs
M/IO#, D/C# and W/R# are the primary bus cycle definition signals. They are driven
valid as the ADS# signal is asserted. M/IO# distinguishes between memory and I/O
cycles, D/C# distinguishes between data and control cycles and W/R# distinguishes
between write and read cycles.
Table 49 shows bus cycle definitions as a function of M/IO#, D/C# and W/R#.
Special bus cycles are discussed in Section 10.3.11.
9.2.5.2 Bus Lock Output (LOCK#)
LOCK# indicates that the Intel
®
Quark SoC X1000 Core is running a read-modify-write
cycle in which the external bus must not be relinquished between the read and write
cycles. Read-modify-write cycles are used to implement memory-based semaphores.
Multiple reads or writes can be locked.
When LOCK# is asserted, the current bus cycle is locked and the Intel
®
Quark SoC
X1000 Core should be allowed exclusive access to the system bus. LOCK# goes active
in the first clock of the first locked bus cycle and goes inactive after ready is returned
indicating the last locked bus cycle.
The Intel
®
Quark SoC X1000 Core does not acknowledge bus hold when LOCK# is
asserted (although it does allow an address hold). LOCK# is active low and is floated
during bus hold. Locked read cycles are not transformed into cache fill cycles if KEN# is
returned active. Refer to Section 10.3.7 for a detailed discussion of locked bus cycles.
Table 49. ADS# Initiated Bus Cycle Definitions
M/IO# D/C# W/R# Bus Cycle Initiated
0 0 0 Interrupt Acknowledge
0 0 1 Halt/Special Cycle
010 I/O Read
011 I/O Write
100 Code Read
1 0 1 Reserved
110 Memory Read
111 Memory Write