Specifications

Intel
®
Quark Core—Hardware Interface
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
158 Order Number: 329679-001US
9.2.10.1 Address Hold Request Input (AHOLD)
AHOLD is the address hold request. It allows another bus master access to the Intel
®
Quark SoC X1000 Core address bus for performing an internal cache invalidation cycle.
Asserting AHOLD forces the Intel
®
Quark SoC X1000 Core to stop driving its address
bus in the next clock. While AHOLD is active only the address bus is floated, the
remainder of the bus can remain active. For example, data can be returned for a
previously specified bus cycle when AHOLD is active. The Intel
®
Quark SoC X1000 Core
does not initiate another bus cycle during address hold. Because the Intel
®
Quark SoC
X1000 Core floats its bus immediately in response to AHOLD, an address hold
acknowledge is not required. If AHOLD is asserted while a bus cycle is in progress and
no readies are returned during the time AHOLD is asserted, the Intel
®
Quark SoC
X1000 Core re-drives the same address (that it originally sent out) once AHOLD is
negated.
AHOLD is recognized during reset. Because the entire cache is invalidated by reset, any
invalidation cycles run during reset is unnecessary. AHOLD is active high and is
provided with a small internal pull-down resistor. It must satisfy the setup and hold
times t
18
and t
19
for proper chip operation. AHOLD also determines whether or not the
built-in self-test features of the Intel
®
Quark SoC X1000 Core are exercised on
assertion of RESET.
9.2.10.2 External Address Valid Input (EADS#)
EADS# indicates that a valid external address has been driven onto the Intel
®
Quark
SoC X1000 Core address pins. This address is used to perform an internal cache
invalidation cycle. The external address is checked with the current cache contents. If
the specified address matches an area in the cache, that area is immediately
invalidated.
An invalidation cycle can be run by asserting EADS# regardless of the state of AHOLD,
HOLD and BOFF#. EADS# is active low and is provided with an internal pull-up resistor.
EADS# must satisfy the setup and hold times t
12
and t
13
for proper chip operation.
9.2.11 Cache Control
9.2.11.1 Cache Enable Input (KEN#)
KEN# is the cache enable pin. KEN# is used to determine whether the data being
returned by the current cycle is cacheable. When KEN# is active and the Intel
®
Quark
SoC X1000 Core generates a cycle that can be cached (most read cycles), the cycle is
transformed into a cache line fill cycle.
A cache line is 16 bytes long. During the first cycle of a cache line fill, the byte-enable
pins should be ignored and data should be returned as if all four byte enables were
asserted. The Intel
®
Quark SoC X1000 Core runs between 4 and 16 contiguous bus
cycles to fill the line depending on the bus data width selected by BS8# and BS16#.
Refer to Section 10.3.3 for a description of cache line fill cycles.
The KEN# input is active low and is provided with a small internal pull-up resistor. It
must satisfy the setup and hold times t
14
and t
15
for proper chip operation.
9.2.11.2 Cache Flush Input (FLUSH#)
The FLUSH# input forces the Intel
®
Quark SoC X1000 Core to flush its entire internal
cache. FLUSH# is active low and must be asserted for one clock only. FLUSH# is
asynchronous but setup and hold times t
20
and t
21
must be met for recognition on any
specific clock.