Specifications

Intel
®
Quark Core—Contents
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
16 Order Number: 329679-001US
78 Encoding of reg Field when the (w) Field is Present in Instruction..................................256
79 2-Bit sreg2 Field.....................................................................................................256
80 3-Bit sreg3 Field.....................................................................................................257
81 Encoding of 16-Bit Address Mode with “mod r/m” Byte ................................................258
82 Encoding of 32-Bit Address Mode with “mod r/m” Byte
(No “s-i-b” Byte Present).........................................................................................259
83 Encoding of 32-Bit Address Mode (“mod r/m” Byte and “s-i-b” Byte Present)..................260
84 Encoding of Operation Direction (d) Field...................................................................260
85 Encoding of Sign-Extend (s) Field .............................................................................261
86 Encoding of Conditional Test (tttn) Field ....................................................................261
87 Encoding of Control or Debug or Test Register (eee) Field............................................262
88 Encoding of Floating-Point Instruction Fields...............................................................263
89 Clock Count Summary.............................................................................................267
90 Task Switch Clock Counts........................................................................................279
91 Interrupt Clock Counts............................................................................................279
92 Notes and Abbreviations (for Table 89 through Table 91).............................................280
93 I/O Instructions Clock Count Summary......................................................................281
94 Floating-Point Clock Count Summary.........................................................................283
95 Intel
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Quark SoC X1000 Core Pin Descriptions...........................................................291
96 Cache Control Bit Encoding and Effect of Control Bits on Entry Select and Set Select
Functionality..........................................................................................................298
97 State Bit Assignments for the Write-Back Enhanced Intel
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Quark SoC X1000 Core..........299
98 Meaning of a Pair of TR6 Protection Bits.....................................................................302
99 TR6 Operation Bit Encoding .....................................................................................302
100 Encoding of Bit 4 of TR7 on Writes............................................................................303
101 Encoding of Bit 4 of TR7 on Lookups .........................................................................303
102 CPUID with PAE/XD/SMEP features implemented ........................................................309
103 Intel
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Quark SoC X1000 CPUID................................................................................310
104 Component Identification.........................................................................................311
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