Specifications

Intel
®
Quark Core—Hardware Interface
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
160 Order Number: 329679-001US
1. The stack fault, invalid operation, and denormal exceptions on all transcendental
instructions, integer arithmetic instructions, FSQRT, FSCALE, FPREM(1), FXTRACT,
FBLD, and FBSTP.
2. Any exceptions on store instructions (including integer store instructions).
The following class of floating-point exceptions assert FERR# only after encountering
the next floating-point instruction:
1. Exceptions other than on all transcendental instructions, integer arithmetic
instructions, FSQRT, FSCALE, FPREM(1), FXTRACT, FBLD, and FBSTP.
2. Any exception on all basic arithmetic, load, compare, and control instructions (i.e.,
all other instructions).
In the event of a pending unmasked floating-point exception the FNINIT, FNCLEX,
FNSTENV, FNSAVE, FNSTSW and FNSTCW instructions assert the FERR# pin. Shortly
after the assertion of the pin, an interrupt window is opened during which the processor
samples and services interrupts, if any. If no interrupts are sampled within this window,
the processor then executes these instructions with the pending unmasked exception.
However, for the FNCLEX, FNINIT, FNSTENV and FNSAVE instructions, the FERR# pin is
de-asserted to enable the execution of these instructions.
9.2.14.2 Ignore Numeric Error Input (IGNNE#)
Note: The implementation of Intel
®
Quark Core on Intel
®
Quark SoC X1000 provides the
capability to control the IGNNE# pin via a register; the default value of the register is
1'b0.
When IGNNE# is asserted and FERR# is still activated, Intel
®
Quark SoC X1000 Core
ignores numeric errors and continue executing non-control floating-point instructions.
When IGNNE# is not asserted and a pending unmasked numeric exception exists
(SW.ES=1), the Intel
®
Quark SoC X1000 Core behaves as follows:
When the Intel
®
Quark SoC X1000 Core encounters the floating-point instructions
FNINIT, FNCLEX, FNSTENV, FNSAVE, FNSTSW or FNSTCW, the processor asserts the
FERR# pin. Subsequently, the processor opens an interrupt sampling window. The
interrupts are checked and serviced during this window. If no interrupts are sampled
within this window the processor then executes these instructions in spite of the
pending unmasked exception.
When the Intel
®
Quark SoC X1000 Core encounters any floating-point instruction other
than FNINIT, FNCLEX, FNSTENV, FNSAVE, FNSTSW or FNSTCW, the processor stops
execution, asserts the FERR# pin, and waits for an external interrupt.
IGNNE# has no effect when the NE bit in control register 0 is set.
The IGNNE# input is active low and provided with a small internal pull-up resistor. This
input is asynchronous, but must meet setup and hold times t
20
and t
21
to ensure
recognition on any specific clock.
9.2.15 Bus Size Control (BS16#, BS8#)
The BS16# and BS8# inputs allow external 16- and 8-bit buses to be supported with a
small number of external components. The Intel
®
Quark SoC X1000 Core samples
these pins every clock. The bus size is determined by the value sampled in the clock
before ready. When asserting BS16# or BS8#, only 16 or 8 bits of the data bus must
be valid. If both BS16# and BS8# are asserted, an 8-bit bus width is selected.
When BS16# or BS8# are asserted, the Intel
®
Quark SoC X1000 Core converts a
larger data request to the appropriate number of smaller transfers. The byte enables
are also modified appropriately for the bus size selected.