Specifications

Intel
®
Quark Core—Hardware Interface
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
164 Order Number: 329679-001US
9.2.17.6 Write-Back/Write-Through (WB/WT#)
WB/WT# enables Enhanced Bus mode (write-back cache). It also allows the system to
define a cached line as write-through or write-back.
WB/WT# is sampled at the falling edge of RESET to determine if Enhanced Bus mode is
enabled (WB/WT# must be driven for two clocks before and two clocks after RESET to
be recognized by the processor). If sampled low or floated, the Write-Back Enhanced
Intel
®
Quark SoC X1000 Core operates in Standard mode. For write-through only
operation, (i.e. Standard mode), WB/WT# does not need to be connected.
In Enhanced Bus mode, WB/WT# allows the system hardware to force any allocated
line to be treated as write-through or write-back. As with cacheability, both the
processor and the external system must agree that a line may be treated as write-back
for the internal cache to be allocated as write-back. The default is always write-
through. The processor's indication of write-back vs. write-through is from the PWT
pin, in which function and timing are the same as in the Standard mode of the Intel
®
Quark SoC X1000 Core.
To define write-back or write-through configuration of a line, WB/WT# is sampled in the
same clock in which the first RDY# or BRDY# is returned during a line fill (allocation)
cycle (see Table 54).
9.2.17.7 Pseudo-Lock Output (PLOCK#)
In the Enhanced Bus mode, PLOCK# is always driven inactive. In this mode, a 64-bit
data read (caused by an FP operand access or a segment descriptor read) is treated as
a multiple cycle read request, which may be a burst or a non-burst access based on
whether BRDY# or RDY# is returned by the system. Because only write-back cycles
(caused by snoop write-back or replacement write-back) are burstable, a 64-bit write is
driven out as two non-burst bus cycles. BLAST# is asserted during both writes. Refer to
Section 10.3 for details on pseudo-locked bus cycles.
9.2.18 Test Signals
The following test signals are available on the Intel
®
Quark SoC X1000 Core.
9.2.18.1 Test Clock (TCK)
TCK is an input to the Intel
®
Quark SoC X1000 Core and provides the clocking function
required by JTAG. TCK is used to clock state information and data into and out of the
component. State select information and data are clocked into the component on the
rising edge of TCK on TMS and TDI, respectively. Data is clocked out of the part on the
falling edge of TCK on TDO.
Table 54. WB/WT# vs. Other Intel
®
Quark Core Signals
Pin Symbol Relation to This Signal
RDY#, BRDY# WB/WT# is sampled with the first RDY# or BRDY#.
PWT
The combination of WB/WT# and PWT determine whether the Write-Back Enhanced
Intel
®
Quark SoC X1000 Core treats the line as WB.
PCD, CACHE#,
KEN#
The state of WB/WT# does not matter if PCD, CACHE# or KEN# define the line to be
non-cacheable.
W/R# WB/WT# is significant only on read fill cycles.
RESET WB/WT# is sampled on the falling edge of RESET to define the cache configuration.