Specifications

Intel
®
Quark Core—Hardware Interface
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
166 Order Number: 329679-001US
9.3.1 Interrupt Logic
The Intel
®
Quark SoC X1000 Core contains a two-clock synchronizer on the interrupt
line. An interrupt request reaches the internal instruction execution unit two clocks
after the INTR pin is asserted if proper setup is provided to the first stage of the
synchronizer.
There is no special logic in the interrupt path other than the synchronizer. The INTR
signal is level sensitive and must remain active for the instruction execution unit to
recognize it. The interrupt is not serviced by the Intel
®
Quark SoC X1000 Core if the
INTR signal does not remain active.
The instruction execution unit looks at the state of the synchronized interrupt signal at
specific clocks during the execution of instructions (if interrupts are enabled). These
specific clocks are at instruction boundaries, or iteration boundaries in the case of
string move instructions. Interrupts are accepted at these boundaries only.
An interrupt must be presented to the Intel
®
Quark SoC X1000 Core INTR pin three
clocks before the end of an instruction for the interrupt to be acknowledged. Presenting
the interrupt three clocks before the end of an instruction allows the interrupt to pass
through the two-clock synchronizer, leaving one clock to prevent the initiation of the
next sequential instruction and begin interrupt service. If the interrupt is not received
in time to prevent the next instruction, it will be accepted at the end of the next
instruction, assuming INTR is still held active.
The longest latency between when an interrupt request is presented on the INTR pin
and when the interrupt service begins is determined as follows:
longest instruction used + the two clocks for synchronization + one clock
required to vector into the interrupt service microcode.
9.3.2 NMI Logic
The NMI pin has a synchronizer much like that used on the INTR line. The NMI logic is
otherwise different from that of the maskable interrupt.
NMI is edge triggered, as opposed to the level triggered INTR signal. The rising edge of
the NMI signal is used to generate the interrupt request. The NMI input need not
remain active until the interrupt is actually serviced. The NMI pin must remain active
only for a single clock if the required setup and hold times are met. NMI operates
properly if it is held active for an arbitrary number of clocks.
The NMI input must be held inactive for at least four clocks after it is asserted to reset
the edge triggered logic. A subsequent NMI may not be generated if the NMI is not held
inactive for at least four clocks after being asserted.
The NMI input is internally masked when the NMI routine is entered. The NMI input
remains masked until an IRET (return from interrupt) instruction is executed. Masking
the NMI signal prevents recursive NMI calls. If another NMI occurs while the NMI is
masked off, the pending NMI is executed after the current NMI is done. Only one NMI
can be pending while NMI is masked.
9.3.3 SMI# Logic
SMI# is edge triggered like NMI, but the interrupt request is generated on the falling-
edge. SMI# is an asynchronous signal, but must meet setup and hold times t
20
and t
21
in order to guarantee recognition on a specific clock. The SMI# input need not remain
active until the interrupt is actually serviced. The SMI# input only needs to remain
active for a single clock if the required setup and hold times are met. SMI# also works
correctly if it is held active for an arbitrary number of clocks.