Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 169
Hardware Interface—Intel
®
Quark Core
9.4.1 Write Buffers and I/O Cycles
Input/Output (I/O) cycles must be handled in a different manner by the write buffers.
I/O reads are never reordered in front of buffered memory writes. This ensures that the
Intel
®
Quark SoC X1000 Core updates all memory locations before reading status from
an I/O device.
The Intel
®
Quark SoC X1000 Core never buffers single I/O writes. When processing an
OUT instruction, internal execution stops until the I/O write completes on the external
bus. This allows time for the external system to drive an invalidate into the Intel
®
Quark SoC X1000 Core or to mask interrupts before the processor progresses to the
instruction following OUT. REP OUTS instructions are buffered.
A read cycle must be generated explicitly to a non-cacheable location in memory to
guarantee that a read bus cycle is performed. This read is not allowed to proceed to the
bus until after the I/O write has completed because I/O writes are not buffered. The
I/O device has time to recover to accept another write during the read cycle.
9.4.2 Write Buffers on Locked Bus Cycles
Locked bus cycles are used for read-modify-write accesses to memory. During a read-
modify-write access, a memory base variable is read, modified and then written back to
the same memory location. It is important that no other bus cycles, generated by other
bus masters or by the Intel
®
Quark SoC X1000 Core itself, be allowed on the external
bus between the read and write portion of the locked sequence.
During a locked read cycle, the Intel
®
Quark SoC X1000 Core always accesses external
memory; it does not look for the location in the on-chip cache. For write cycles, data is
written to the internal cache (if cache hit) and the external memory. All data pending in
the Intel
®
Quark SoC X1000 Core's write buffers is written to memory before a locked
cycle is allowed to proceed to the external bus.
The Intel
®
Quark SoC X1000 Core asserts LOCK# after the write buffers are emptied
during a locked bus cycle. With LOCK# asserted, the processor reads the data,
operates on the data, and places the results in a write buffer. The contents of the write
buffer are then written to external memory. LOCK# becomes inactive after the write
part of the locked cycle.
9.5 Reset and Initialization
The Intel
®
Quark SoC X1000 Core has a built in self test (BIST) that can be run during
reset. BIST is invoked when the AHOLD pin is asserted for one clock before and de-
asserted one clock after RESET is de-asserted. RESET must be active for 15 clocks with
or without BIST being enabled. To ensure proper results, neither FLUSH# nor SRESET
can be asserted while BIST is executing.
The Intel
®
Quark SoC X1000 Core registers have the values shown in Table 55 after
RESET is performed. The EAX register contains information on the success or failure of
the BIST if the self test is executed. The DX register always contains a component
identifier at the conclusion of RESET. The upper byte of DX (DH) contains 04 and the
lower byte (DL) contains the revision identifier (see Table 56).
RESET forces the Intel
®
Quark SoC X1000 Core to terminate all execution and local bus
activity. No instruction or bus activity occurs as long as RESET is active.
All entries in the cache are invalidated by RESET.