Specifications

Intel
®
Quark Core—Hardware Interface
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
170 Order Number: 329679-001US
9.5.1 Floating-Point Register Values
In addition to the register values listed above, Intel
®
Quark SoC X1000 Core has the
floating-point register values shown in Table 57.
If the BIST is performed, the floating-point registers are initialized as if the
FINIT/FNINIT (initialize processor) instruction were executed. If the BIST is not
executed, the floating-point registers are unchanged.
The Intel
®
Quark SoC X1000 Core starts executing instructions at location FFFFFFF0H
after RESET. When the first Inter Segment Jump or Call is executed, address lines
A[31:20] drop low for CS-relative memory cycles, and the Intel
®
Quark SoC X1000
Core executes instructions only in the lower 1 Mbyte of physical memory. This allows
the system designer to use ROM at the top of physical memory to initialize the system
and take care of RESETs.
Table 55. Register Values after Reset
Register
Initial Value
(BIST)
Initial Value
(No BIST)
EAX Zero (Pass) Undefined
ECX Undefined Undefined
EDX 0400 + Revision ID 0400 + Revision ID
EBX Undefined Undefined
ESP Undefined Undefined
EBP Undefined Undefined
ESI Undefined Undefined
EDI Undefined Undefined
EFLAGS 00000002h 00000002h
EIP 0FFF0h 0FFF0h
ES 0000h 0000h
CS F000h F000h
SS 0000h 0000h
DS 0000h 0000h
FS 0000h 0000h
GS 0000h 0000h
IDTR
Base = 0,
Limit = 3FFh
Base = 0,
Limit = 3FFh
CR0 60000010h 60000010h
DR7 00000000h 00000000h
Table 56. Floating-Point Values after Reset (Sheet 1 of 2)
Register
Initial Value
(BIST)
Initial Value
(No BIST)
CW 037Fh Unchanged
SW 0000h Unchanged
TW FFFFh Unchanged
FIP 00000000h Unchanged