Specifications
Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 175
Hardware Interface—Intel
®
Quark Core
M/IO# = 0, D/C# = 0, W/R# = 1, address bus = 0000 0010H (A
4
= 1), BE3:0# =
1011, data bus = undefined
The latency between a STPCLK# request and the Stop Grant bus cycle depends on the
current instruction, the amount of data in the processor write buffers, and the system
memory performance (see Figure 73).
Figure 73. Stop Clock Protocol
9.6.2 Pin State During Stop Grant
During the Stop Grant state, most output and input/output signals of the processor
maintain their previous condition (the level they held when entering the Stop Grant
state). The data and data parity signals are three-stated. In response to HOLD being
driven active during the Stop Grant state (when the CLK input is running), the
processor generates HLDA and three-states all output and input/output signals that are
three-stated during the HOLD/HLDA state. After HOLD is de-asserted, all signals return
to their prior state before the HOLD/HLDA sequence.
In order to achieve the lowest possible power consumption during the Stop Grant state,
the system designer must ensure that the input signals with pull-up resistors are not
driven low and the input signals with pull-down resistors are not driven high.
All inputs except the data bus pins must be driven to the power supply rails to ensure
the lowest possible current consumption during Stop Grant or Stop Clock states. For
compatibility with future processors, data pins should be driven low to achieve the
lowest possible power consumption. Pull-down resistors/bus keepers are needed to
minimize leakage current.
If HOLD is asserted during the Stop Grant state, all pins that are normally floated
during HLDA are still floated by the processor. The floated pins should be driven to a
low level (see Table 58).
CLK
STPCLK#
ADDR
RDY#
Stop Grant Bus Cycle
T
SU
T
HD
Table 58. Pin State during Stop Grant Bus State (Sheet 1 of 2)
Signal Type State
A[3:2] O Previous state
A[31:4] I/O Previous state
D[31:0] I/O Floated
BE[3:0]# O Previous state