Specifications

Intel
®
Quark Core—Hardware Interface
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
176 Order Number: 329679-001US
9.6.3 Write-Back Enhanced Intel
®
Quark SoC X1000 Core Pin States
During Stop Grant State
During the Stop Grant state, most output signals of the processor maintain their
previous condition, which is the level they held when entering the Stop Grant state. The
data bus and data parity signals also maintain their previous state. In response to
HOLD being driven active during the Stop Grant state when the CLK input is running,
the Write-Back Enhanced Intel
®
Quark SoC X1000 Core generates HLDA and three-
states all output and input/output signals that are three-stated during the HOLD/HLDA
state. After HOLD is de-asserted, all signals return to the state they were in prior to the
HOLD/HLDA sequence.
All inputs should be driven to the power supply rails to ensure the lowest possible
current consumption during the Stop Grant or Stop Clock states (see Table 59).
DP[3:0] I/O Floated
W/R#, D/C#, M/IO# O Previous state
ADS# O Inactive
LOCK#, PLOCK# O Inactive
BREQ O Previous state
HLDA O As per HOLD
BLAST# O Previous state
FERR# O Previous state
PCD, PWT O Previous state
PCHK# O Previous state
PWT, PCD O Previous state
SMIACT# O Previous state
Table 58. Pin State during Stop Grant Bus State (Sheet 2 of 2)
Signal Type State
Table 59. Write-Back Enhanced Intel
®
Quark SoC X1000 Core Pin States
during Stop Grant Bus Cycle (Sheet 1 of 2)
Signal Type State
A[3:2] O Previous state
A[31:4] I/O Previous state
D[31:0] I/O Previous state
BE[3:0]# O Previous state
DP[3:0] I/O Previous state
W/R#, D/C#, M/IO# O Previous state
ADS# O Inactive (high)
LOCK#, PLOCK# O Inactive (high)
BREQ O Previous state
HLDA O As per HOLD
Notes:
1. For the case of snoop cycles (via EADS#) during Stop Grant state, both HITM#
and CACHE# may go active depending on the snoop hit in the internal cache.
2. During Stop Grant state, AHOLD, HOLD, BOFF# and EADS# are serviced normally.