Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 185
Bus Operation—Intel
®
Quark Core
Figure 77. Physical Memory and I/O Spaces
10.1.1.1 Memory and I/O Space Organization
The Intel
®
Quark SoC X1000 Core datapath to memory and input/output (I/O) spaces
can be 8, 16, or 32 bits wide. The byte enable signals, BE[3:0]#, allow byte granularity
when addressing any memory or I/O structure, whether 8, 16, or 32 bits wide.
The Intel
®
Quark SoC X1000 Core includes bus control pins, BS16# and BS8#, which
allow direct connection to 16- and 8-bit memories and I/O devices. Cycles of 32-, 16-
and 8-bits may occur in any sequence, since the BS8# and BS16# signals are sampled
during each bus cycle.
Memory and I/O spaces that are 32-bit wide are organized as arrays of four bytes each.
Each four bytes consists of four individually addressable bytes at consecutive byte
addresses (see Figure 78). The lowest addressed byte is associated with data signals
D[7:0]; the highest-addressed byte with D[31:24]. Each 4 bytes begin at an address
that is divisible by four.
Table 61. Generating A[31:0] from BE[3:0]# and A[31:A2]
Intel
®
Quark SoC X1000 Core Address Signals
Physical Address BE3# BE2# BE1# BE0#
A31 ... A2 A1 A0
A31 ... A2 0 0 X X X 0
A31 ... A2 0 1 X X 0 1
A31 ... A2 1 0 X 0 1 1
A31...A2110111
Physical
Memory
4 Gbyte
Not
Accessible
64 Kbyte
{
Accessible
Programmed
I/O Space
0000FFFFH
00000000H
00000000H
Physical Memory
Space
I/O Space
FFFFFFFFH
Not
Accessible