Specifications

Intel
®
Quark Core—Bus Operation
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
188 Order Number: 329679-001US
In 32-bit physical memories, such as the one shown in Figure 79, each 4-byte word
begins at a byte address that is a multiple of four. A[31:2] are used as a 4-byte word
select. BE[3:0]# select individual bytes within the 4-byte word. BS8# and BS16# are
deasserted for all bus cycles involving the 32-bit array.
For 16- and 8-bit memories, byte swapping logic is required for routing data to the
appropriate data lines and logic is required for generating BHE#, BLE# and A1. In
systems where mixed memory widths are used, extra address decoding logic is
necessary to assert BS16# or BS8#.
Figure 79. Intel
®
Quark SoC X1000 Core with 32-Bit Memory
Figure 80 shows the Intel
®
Quark SoC X1000 Core address bus interface to 32-, 16-
and 8-bit memories. To address 16-bit memories the byte enables must be decoded to
produce A1, BHE# and BLE# (A0). For 8-bit wide memories the byte enables must be
decoded to produce A0 and A1. The same byte select logic can be used in 16- and 8-bit
systems, because BLE# is exactly the same as A0 (see Table 64).
Figure 80. Addressing 16- and 8-Bit Memories
BE[3:0]# can be decoded as shown in Table 64. The byte select logic necessary to
generate BHE# and BLE# is shown in Figure 81.
Intel® Quark
Core
32-Bit
Memory
Data Bus (D[31:0])
32
Address Bus
(BE[3:0]#, A[31:2])
BS8#
BS16#
“HIGH” “HIGH”
Intel® Quark
Core
BS16#
BS8#
Address Bus (A[31:2], BE[3:0]#)
A[31:2]
BE[3:0]#
BHE#, BLE#, A1
A0 (BLE#), A1
A[31:2]
8-Bit Memory
16-Bit Memory
32-Bit Memory
Byte
Select Logic
Address
Decode