Specifications

Intel
®
Quark Core—Bus Operation
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
194 Order Number: 329679-001US
Figure 84. Single Intel
®
Quark Core with DMA
Figure 85 shows more than one primary bus master and two secondary masters, and
the arbitration logic is more complex. The arbitration logic resolves bus contention by
ensuring that all device requests are serviced one at a time using either a fixed or a
rotating scheme. The arbitration logic then passes information to the Intel
®
Quark SoC
X1000 Core, which ultimately releases the bus. The arbitration logic receives bus
control status information via the HOLD and HLDA signals and relays it to the
requesting devices.
Intel® Quark
Core
DMA
MEM
I/O
Address Bus
Data Bus
Control Bus