Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 203
Bus Operation—Intel
®
Quark Core
Figure 90. Non-Burst, Cacheable Cycles
10.3.3.3 Burst Cacheable Cycles
Figure 91 illustrates a burst mode cache fill. As in Figure 90, the transfer becomes a
cache line fill when the external system asserts KEN# at the end of the first clock in the
cycle.
The external system informs the Intel
®
Quark SoC X1000 Core that it will burst the line
in by asserting BRDY# at the end of the first cycle in the transfer.
Note that during a burst cycle, ADS# is only driven with the first address.
CLK
ADS#
A31–A2
M/IO#
D/C#
W/R#
BE3#–BE0#
KEN#
RDY#
BLAST#
DATA
Ti T1 T2 T1 T2 T1 T2 T1 T2 Ti
†
To Processor
BRDY#
†
†
††
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