Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 207
Bus Operation—Intel
®
Quark Core
Figure 94. Burst Cycle Showing Order of Addresses
The sequences shown in Table 67 accommodate systems with 64-bit buses as well as
systems with 32-bit data buses. The sequence applies to all bursts, regardless of
whether the purpose of the burst is to fill a cache line, perform a 64-bit read, or
perform a pre-fetch. If either BS8# or BS16# is asserted, the Intel
®
Quark SoC X1000
Core completes the transfer of the current 32-bit word before progressing to the next
32-bit word. For example, a BS16# burst to address 4 has the following order:
4-6-0-2-C-E-8-A.
10.3.4.3 Interrupted Burst Cycles
Some memory systems may not be able to respond with burst cycles in the order
defined in Table 67. To support these systems, the Intel
®
Quark SoC X1000 Core allows
a burst cycle to be interrupted at any time. The Intel
®
Quark SoC X1000 Core
automatically generates another normal bus cycle after being interrupted to complete
the data transfer. This is called an interrupted burst cycle. The external system can
respond to an interrupted burst cycle with another burst cycle.
The external system can interrupt a burst cycle by asserting RDY# instead of BRDY#.
RDY# can be asserted after any number of data cycles terminated with BRDY#.
An example of an interrupted burst cycle is shown in Figure 95. The Intel
®
Quark SoC
X1000 Core immediately asserts ADS# to initiate a new bus cycle after RDY# is
asserted. BLAST# is deasserted one clock after ADS# begins the second bus cycle,
indicating that the transfer is not complete.
242202-039
CLK
ADS#
A31–A2
RDY#
BLAST#
DATA
Ti
To Processor
T1 T2 T2 T2 T2 Ti
KEN#
BRDY#
104 100 10C 108
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