Specifications

Intel
®
Quark Core—Bus Operation
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
208 Order Number: 329679-001US
Figure 95. Interrupted Burst Cycle
KEN# need not be asserted in the first data cycle of the second part of the transfer
shown in Figure 96. The cycle had been converted to a cache fill in the first part of the
transfer and the Intel
®
Quark SoC X1000 Core expects the cache fill to be completed.
Note that the first half and second half of the transfer in Figure 95 are both two-cycle
burst transfers.
The order in which the Intel
®
Quark SoC X1000 Core requests operands during an
interrupted burst transfer is shown by Table 66. Mixing RDY# and BRDY# does not
change the order in which operand addresses are requested by the Intel
®
Quark SoC
X1000 Core.
An example of the order in which the Intel
®
Quark SoC X1000 Core requests operands
during a cycle in which the external system mixes RDY# and BRDY# is shown in
Figure 96. The Intel
®
Quark SoC X1000 Core initially requests a transfer beginning at
location 104. The transfer becomes a cache line fill when the external system asserts
KEN#. The first cycle of the cache fill transfers the contents of location 104 and is
terminated with RDY#. The Intel
®
Quark SoC X1000 Core drives out a new request (by
asserting ADS#) to address 100. If the external system terminates the second cycle
with BRDY#, the Intel
®
Quark SoC X1000 Core next requests/expects address 10C.
The correct order is determined by the first cycle in the transfer, which may not be the
first cycle in the burst if the system mixes RDY# with BRDY#.
242202-067
CLK
ADS#
A31–A2
BRDY#
BLAST#
DATA
Ti T1 T2 Ti
To Processor
T2 T1 T2 T2
KEN#
RDY#
104 100 10C 108
†
†
††
†