Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 209
Bus Operation—Intel
®
Quark Core
Figure 96. Interrupted Burst Cycle with Non-Obvious Order of Addresses
10.3.5 8- and 16-Bit Cycles
The Intel
®
Quark SoC X1000 Core supports both 16- and 8-bit external buses through
the BS16# and BS8# inputs. BS16# and BS8# allow the external system to specify, on
a cycle-by-cycle basis, whether the addressed component can supply 8, 16 or 32 bits.
BS16# and BS8# can be used in burst cycles as well as non-burst cycles. If both
BS16# and BS8# are asserted for any bus cycle, the Intel
®
Quark SoC X1000 Core
responds as if only BS8# is asserted.
The timing of BS16# and BS8# is the same as that of KEN#. BS16# and BS8# must be
asserted before the first RDY# or BRDY# is asserted. Asserting BS16# and BS8# can
force the Intel
®
Quark SoC X1000 Core to run additional cycles to complete what would
have been only a single 32-bit cycle. BS8# and BS16# may change the state of
BLAST# when they force subsequent cycles from the transfer.
Figure 97 shows an example in which BS8# forces the Intel
®
Quark SoC X1000 Core to
run two extra cycles to complete a transfer. The Intel
®
Quark SoC X1000 Core issues a
request for 24 bits of information. The external system asserts BS8#, indicating that
only eight bits of data can be supplied per cycle. The Intel
®
Quark SoC X1000 Core
issues two extra cycles to complete the transfer.
242202-068
CLK
ADS#
A31–A2
BRDY#
BLAST#
DATA
Ti T1 T2 Ti
To Processor
T1 T2 T2 T2
KEN#
RDY#
104 100 10C 108
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