Specifications

Intel
®
Quark Core—Bus Operation
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
216 Order Number: 329679-001US
Figure 103. System with Second-Level Cache
If the system asserts EADS# before the first data in the line fill is returned to the Intel
®
Quark SoC X1000 Core, the system must return data consistent with the new data in
the external memory upon resumption of the line fill after the invalidation cycle. This is
illustrated by the asserted EADS# signal labeled “1” in Figure 104.
If the system asserts EADS# at the same time or after the first data in the line fill is
returned (in the same clock that the first RDY# or BRDY# is asserted or any
subsequent clock in the line fill) the data is read into the Intel
®
Quark SoC X1000 Core
input buffers but it is not stored in the on-chip cache. This is illustrated by asserted
EADS# signal labeled “2” in Figure 104. The stale data is used to satisfy the request
that initiated the cache fill cycle.
Intel® Quark
Core
Second-Level
Cache
System Bus
External
Memory
External Bus
Master
Address, Data and
Control Bus
Address, Data and
Control Bus