Specifications

Intel

Quark Core—Bus Operation

Intel

Quark SoC X1000 Core

Developer’s Manual October 2013

218 Order Number: 329679-001US

Figure 105. HOLD/HLDA Cycles

Note that HOLD is recognized during un-aligned writes (less than or equal to 32 bits)

with BLAST# being asserted for each write. For a write greater than 32-bits or an un-

aligned write, HOLD# recognition is prevented by PLOCK# getting asserted. However,

HOLD is recognized during non-cacheable, non-burstable code prefetches even though

PLOCK# is asserted.

For cacheable and non-burst or burst cycles, HOLD is acknowledged during backoff only

if HOLD and BOFF# are asserted during an active bus cycle (after ADS# asserted) and

before the first RDY# or BRDY# has been asserted (see Figure 106). The order in which

HOLD and BOFF# are asserted is unimportant (as long as both are asserted prior to the

first RDY#/BRDY# asserted by the system). Figure 106 shows the case where HOLD is

asserted first; HOLD could be asserted simultaneously or after BOFF# and still be

acknowledged.

The pins floated during bus hold are: BE[3:0]#, PCD, PWT, W/R#, D/C#, M/O#,

LOCK#, PLOCK#, ADS#, BLAST#, D[31:0], A[31:2], and DP[3:0].

242202-146

CLK

ADS#

A31–A2

M/IO#

D/C#

W/R#

BE3#–BE0#

RDY#

DATA

HLDA

From Processor

Ti T1 T2 Ti Ti T1

‡

HOLD

‡