Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 219
Bus Operation—Intel
®
Quark Core
Figure 106. HOLD Request Acknowledged during BOFF#
10.3.10 Interrupt Acknowledge
The Intel
®
Quark SoC X1000 Core generates interrupt acknowledge cycles in response
to maskable interrupt requests that are generated on the interrupt request input
(INTR) pin. Interrupt acknowledge cycles have a unique cycle type generated on the
cycle type pins.
An example of an interrupt acknowledge transaction is shown in Figure 107. Interrupt
acknowledge cycles are generated in locked pairs. Data returned during the first cycle
is ignored. The interrupt vector is returned during the second cycle on the lower 8 bits
of the data bus. The Intel
®
Quark SoC X1000 Core has 256 possible interrupt vectors.
The state of A2 distinguishes the first and second interrupt acknowledge cycles. The
byte address driven during the first interrupt acknowledge cycle is 4 (A[31:3] low, A2
high, BE[3:1]# high, and BE0# low). The address driven during the second interrupt
acknowledge cycle is 0 (A[31:2] low, BE[3:1]# high, BE0# low).
Each of the interrupt acknowledge cycles is terminated when the external system
asserts RDY# or BRDY#. Wait states can be added by holding RDY# or BRDY#
deasserted. The Intel
®
Quark SoC X1000 Core automatically generates four idle clocks
between the first and second cycles to allow for 8259A recovery time.
242202-095
CLK
ADS#
M/IO#
D/C#
KEN#
BRDY#
RDY#
W/R#
HOLD
HLDA
BOFF#
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