Specifications

Intel
®
Quark Core—Bus Operation
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
220 Order Number: 329679-001US
Figure 107. Interrupt Acknowledge Cycles
10.3.11 Special Bus Cycles
The Intel
®
Quark SoC X1000 Core provides special bus cycles to indicate that certain
instructions have been executed, or certain conditions have occurred internally. The
special bus cycles are identified by the status of the pins shown in Table 68.
During these cycles the address bus is driven low while the data bus is undefined.
Two of the special cycles indicate halt or shutdown. Another special cycle is generated
when the Intel
®
Quark SoC X1000 Core executes an INVD (invalidate data cache)
instruction and could be used to flush an external cache. The Write Back cycle is
generated when the Intel
®
Quark SoC X1000 Core executes the WBINVD (write-back
invalidate data cache) instruction and could be used to synchronize an external write-
back cache.
The external hardware must acknowledge these special bus cycles by asserting RDY#
or BRDY#.
10.3.11.1 HALT Indication Cycle
The Intel
®
Quark SoC X1000 Core halts as a result of executing a HALT instruction. A
HALT indication cycle is performed to signal that the processor has entered into the
HALT state. The HALT indication cycle is identified by the bus definition signals in
special bus cycle state and by a byte address of 2. BE0# and BE2# are the only signals
that distinguish HALT indication from shutdown indication, which drives an address of
0. During the HALT cycle, undefined data is driven on D[31:0]. The HALT indication
cycle must be acknowledged by RDY# asserted.
A halted Intel
®
Quark SoC X1000 Core resumes execution when INTR (if interrupts are
enabled), NMI, or RESET is asserted.
CLK
ADS#
ADDR
RDY#
DATA
Ti T1 T2 Ti Ti T1 T2 Ti
To Processor
†
LOCK#
4 Clocks
†
04
00
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