Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 221
Bus Operation—Intel
®
Quark Core
10.3.11.2 Shutdown Indication Cycle
The Intel
®
Quark SoC X1000 Core shuts down as a result of a protection fault while
attempting to process a double fault. A shutdown indication cycle is performed to
indicate that the processor has entered a shutdown state. The shutdown indication
cycle is identified by the bus definition signals in special bus cycle state and a byte
address of 0.
10.3.11.3 Stop Grant Indication Cycle
A special Stop Grant bus cycle is driven to the bus after the processor recognizes the
STPCLK# interrupt. The definition of this bus cycle is the same as the HALT cycle
definition for the Intel
®
Quark SoC X1000 Core, with the exception that the Stop Grant
bus cycle drives the value 0000 0010H on the address pins. The system hardware must
acknowledge this cycle by asserting RDY# or BRDY#. The processor does not enter the
Stop Grant state until either RDY# or BRDY# has been asserted. (See Figure 108.)
The Stop Grant Bus Cycle is defined as follows:
M/IO# = 0, D/C# = 0, W/R# = 1, Address Bus = 0000 0010H (A4 = 1), BE[3:0]# =
1011, Data bus = undefined.
The latency between a STPCLK# request and the Stop Grant bus cycle is dependent on
the current instruction, the amount of data in the processor write buffers, and the
system memory performance.
Figure 108. Stop Grant Bus Cycle
Table 68. Special Bus Cycle Encoding
Cycle Name M/IO# D/C# W/R# BE[3:0]# A4-A2
Write-Back† 0010111000
First Flush Ack Cycle† 0 0 1 0111 001
Flush† 0011101000
Second Flush Ack Cycle† 0 0 1 1101 001
Shutdown 0011110000
HALT 0011011000
Stop Grant Ack Cycle 0 0 1 1011 100
† These cycles are specific to the Write-Back Enhanced Intel
®
Quark SoC X1000 Core.
STPCLK#
CLK
A4401-01
Stop Grant Cycle
BRDY# or RDY#
ADDR Data
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