Specifications

Intel
®
Quark Core—Bus Operation
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
222 Order Number: 329679-001US
10.3.12 Bus Cycle Restart
In a multi-master system, another bus master may require the use of the bus to enable
the Intel
®
Quark SoC X1000 Core to complete its current bus request. In this situation,
the Intel
®
Quark SoC X1000 Core must restart its bus cycle after the other bus master
has completed its bus transaction.
A bus cycle may be restarted if the external system asserts the backoff (BOFF#) input.
The Intel
®
Quark SoC X1000 Core samples the BOFF# pin every clock cycle. When
BOFF# is asserted, the Intel
®
Quark SoC X1000 Core floats its address, data, and
status pins in the next clock (see Figure 109 and Figure 110). Any bus cycle in progress
when BOFF# is asserted is aborted and any data returned to the processor is ignored.
The pins that are floated in response to BOFF# are the same as those that are floated
in response to HOLD. HLDA is not generated in response to BOFF#. BOFF# has higher
priority than RDY# or BRDY#. If either RDY# or BRDY# are asserted in the same clock
as BOFF#, BOFF# takes effect.
Figure 109. Restarted Read Cycle
242202-097
CLK
Ti T1 T2 Tb Tb T1b T2 T2 T2 T2 T2
ADS#
A31–A2
M/IO#
D/C#
BE3#–BE0#
KEN#
RDY#
BLAST#
DATA
To Processor
†
BRDY#
BOFF#
100 100 104 108 10C
†
†
†
†