Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 223
Bus Operation—Intel
®
Quark Core
Figure 110. Restarted Write Cycle
The device asserting BOFF# is free to run cycles while the Intel
®
Quark SoC X1000
Core bus is in its high impedance state. If backoff is requested after the Intel
®
Quark
SoC X1000 Core has started a cycle, the new master should wait for memory to assert
RDY# or BRDY# before assuming control of the bus. Waiting for RDY# or BRDY#
provides a handshake to ensure that the memory system is ready to accept a new
cycle. If the bus is idle when BOFF# is asserted, the new master can start its cycle two
clocks after issuing BOFF#.
The external memory can view BOFF# in the same manner as BLAST#. Asserting
BOFF# tells the external memory system that the current cycle is the last cycle in a
transfer.
The bus remains in the high impedance state until BOFF# is deasserted. Upon
negation, the Intel
®
Quark SoC X1000 Core restarts its bus cycle by driving out the
address and status and asserting ADS#. The bus cycle then continues as usual.
Asserting BOFF# during a burst, BS8#, or BS16# cycle forces the Intel
®
Quark SoC
X1000 Core to ignore data returned for that cycle only. Data from previous cycles is still
valid. For example, if BOFF# is asserted on the third BRDY# of a burst, the Intel
®
Quark SoC X1000 Core assumes the data returned with the first and second BRDY# is
correct and restarts the burst beginning with the third item. The same rule applies to
transfers broken into multiple cycles by BS8# or BS16#.
Asserting BOFF# in the same clock as ADS# causes the Intel
®
Quark SoC X1000 Core
to float its bus in the next clock and leave ADS# floating low. Because ADS# is floating
low, a peripheral may think that a new bus cycle has begun even though the cycle was
aborted. There are two possible solutions to this problem. The first is to have all
devices recognize this condition and ignore ADS# until RDY# is asserted. The second
approach is to use a “two clock” backoff: in the first clock AHOLD is asserted, and in the
second clock BOFF# is asserted. This guarantees that ADS# is not floating low. This is
necessary only in systems where BOFF# may be asserted in the same clock as ADS#.
242202-147
CLK
ADS#
ADDR
SPEC
BRDY#
DATA
Ti T1 T2 Ti
From Processor
‡
Tb Tb T1b T2
BOFF#
RDY#
100 100
‡
‡