Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 23
Architectural Overview—Intel
®
Quark Core
In addition to these basic data types, the Intel
®
Quark SoC X1000 Core supports two
larger units of memory: pages and segments. Memory can be divided up into one or
more variable-length segments, which can be swapped to disk or shared between
programs. Memory can also be organized into one or more 4-Kbyte pages. Both
segmentation and paging can be combined, gaining the advantages of both systems.
The Intel
®
Quark SoC X1000 Core supports both pages and segments in order to
provide maximum flexibility to the system designer. Segmentation and paging are
complementary. Segmentation is useful for organizing memory in logical modules, and
as such is a tool for the application programmer, while pages are useful for the system
programmer for managing the physical memory of a system.
3.3.1 Address Spaces
The Intel
®
Quark SoC X1000 Core has three distinct address spaces: logical, linear, and
physical. A logical address (also known as a virtual address) consists of a selector and
an offset. A selector is the contents of a segment register. An offset is formed by
summing all of the addressing components (BASE, INDEX, DISPLACEMENT) discussed
in Section 3.5.3 into an effective address. Because each task on the Intel
®
Quark SoC
X1000 Core has a maximum of 16 K (2
14
- 1) selectors, and offsets can be 4 Gbytes
(2
32
bits), this gives a total of 2
46
bits or 64 terabytes of logical address space per task.
The programmer sees this virtual address space.
The segmentation unit translates the logical address space into a 32-bit linear address
space. If the paging unit is not enabled then the 32-bit linear address corresponds to
the physical address. The paging unit translates the linear address space into the
physical address space. The physical address is what appears on the address pins.
The primary difference between Real Mode and Protected Mode is how the
segmentation unit performs the translation of the logical address into the linear
address. In Real Mode, the segmentation unit shifts the selector left four bits and adds
the result to the offset to form the linear address. While in Protected Mode every
selector has a linear base address associated with it. The linear base address is stored
in one of two operating system tables (i.e., the Local Descriptor Table or Global
Descriptor Table). The selector's linear base address is added to the offset to form the
final linear address.
Figure 2 shows the relationship between the various address spaces.