Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 231
Bus Operation—Intel
®
Quark Core
Figure 113. Snoop Cycle Invalidating a Modified Line
The next ADS# for a new cycle can occur immediately after the last RDY# or BRDY# of
the write-back cycle. The Write-Back Enhanced Intel
®
Quark SoC X1000 Core does not
guarantee a dead clock between cycles unless the second cycle is a snoop-forced write-
back cycle. This allows snoop-forced write-backs to be backed off (BOFF#) when
snooping under AHOLD.
HITM# is guaranteed to remain asserted until the RDY# or BRDY# signals
corresponding to the last doubleword of the write-back cycle is returned. HITM# is de-
asserted from the clock edge in which the last BRDY# or RDY# for the snoop write-
back cycle is asserted. The write-back cycle could be a burst or non-burst cycle. In
either case, 16 bytes of data corresponding to the modified line that has a snoop hit is
written back.
10.4.3.2.1 Snoop under AHOLD Overlaying a Line-Fill Cycle
The assertion of AHOLD during a line fill is allowed on the Write-Back Enhanced Intel
®
Quark SoC X1000 Core. In this case, when a snoop cycle is overlaid by an on-going
line-fill cycle, the chipset must generate the burst addresses internally for the line fill to
complete, because the address bus has the valid snoop address. The write-back mode
is more complex compared to the write-through mode because of the possibility of a
line being written back. Figure 114 shows a snoop cycle overlaying a line-fill cycle,
when the snooped line is not the same as the line being filled.
242202-150
CLK
AHOLD
EADS#
INV
HITM#
BRDY#
CACHE#
12345678910111213
BLAST#
A31–A4
*
**
A3–A2 0 4 8 C
ADS#
W/R#
To Processor
Write-back from Processor
*
**