Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 239
Bus Operation—Intel
®
Quark Core
Figure 120. Snoop using HOLD during a Non-Cacheable, Non-Burstable Code Prefetch
10.4.3.6 Snoop under HOLD during Replacement Write-Back
Collision of snoop cycles under a HOLD during the replacement write-back cycle can
never occur, because HLDA is asserted only after the replacement write-back cycle
(burst or non-burst) is completed.
10.4.4 Locked Cycles
In both Standard and Enhanced Bus modes, the Write-Back Enhanced Intel
®
Quark
SoC X1000 Core architecture supports atomic memory access. A programmer can
modify the contents of a memory variable and be assured that the variable is not
accessed by another bus master between the read of the variable and the update of
that variable. This function is provided for instructions that contain a LOCK prefix, and
also for instructions that implicitly perform locked read modify write cycles. In
hardware, the LOCK function is implemented through the LOCK# pin, which indicates
242202-157
CLK
HOLD
EADS#
HITM#
A31–A4
A3–A2
ADS#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
BLAST#
CACHE#
To Processor
W/R#
0 4 8 C
INV
RDY#
BRDY#
HLDA
C0 4 8
Prefetch Cycle
Write Back Cycle
Prefetch
Cont.
†
†