Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 241
Bus Operation—Intel
®
Quark Core
10.4.4.1 Snoop/Lock Collision
If there is a snoop cycle overlaying a locked cycle, the snoop write-back cycle fractures
the locked cycle. As shown in Figure 122, after the read portion of the locked cycle is
completed, the snoop write-back starts under HITM#. After the write-back is
completed, the locked cycle continues. But during all this time (including the write-back
cycle), the LOCK# signal remains asserted.
Because HOLD is not acknowledged if LOCK# is asserted, snoop-lock collisions are
restricted to AHOLD and BOFF# snooping.
Figure 122. Snoop Cycle Overlaying a Locked Cycle
10.4.5 Flush Operation
The Write-Back Enhanced Intel
®
Quark SoC X1000 Core executes a flush operation
when the FLUSH# pin is asserted, and no outstanding bus cycles, such as a line fill or
write back, are being processed. In the Enhanced Bus mode, the processor first writes
back all the modified lines to external memory. After the write-back is completed, two
special cycles are generated, indicating to the external system that the write-back is
done. All lines in the internal cache are invalidated after all the write-back cycles are
done. Depending on the number of modified lines in the cache, the flush could take a
minimum of 1280 bus clocks (2560 processor clocks) and up to a maximum of 5000+
bus clocks to scan the cache, perform the write backs, invalidate the cache, and run the
flush acknowledge cycles. FLUSH# is implemented as an interrupt in the Enhanced Bus
mode, and is recognized only on an instruction boundary. Write-back system designs
should look for the flush acknowledge cycles to recognize the end of the flush
operation. Figure 123 shows the flush operation of the Write-Back Enhanced Intel
®
Quark SoC X1000 Core when configured in the Enhanced Bus mode.
242202-159
CLK
ADS#
RDY#
BRDY#
AHOLD
ADDR
EADS#
HITM#
W/R#
To Processor
From Processor
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Write
0 4 8 C
CACHE#
LOCK#
WB1 WB2 WB3 WB4
Write
Read
WB
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