Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 249
Debugging Support—Intel
®
Quark Core
Note that instruction execution breakpoints are taken as faults (i.e., before the
instruction executes), but data breakpoints are taken as traps (i.e., after the data
transfer takes place).
Using LENi and RWi to Set Data Breakpoint i
A data breakpoint can be set up by writing the linear address into DRi (i = 0–3). For
data breakpoints, RWi can equal 01 (write-only) or 11 (write/read). LEN can equal 00,
01, or 11.
When a data access entirely or partly falls within the data breakpoint field, the data
breakpoint condition has occurred, and if the breakpoint is enabled, an exception 1 trap
occurs.
Using LENi and RWi to Set Instruction Execution Breakpoint i
An instruction execution breakpoint can be set up by writing the address of the
beginning of the instruction (including prefixes if any) into DRi (i = 0–3). RWi must
equal 00 and LEN must equal 00 for instruction execution breakpoints.
When the instruction beginning at the breakpoint address is about to be executed, the
instruction execution breakpoint condition has occurred, and if the breakpoint is
enabled, an exception 1 fault occurs before the instruction is executed.
Note that an instruction execution breakpoint address must be equal to the beginning
byte address of an instruction (including prefixes) for the instruction execution
breakpoint to occur.
GD (Global Debug Register access detect)
The Debug Registers can be accessed only in Real Mode or at privilege level 0 in
Protected Mode. The GD bit, when set, provides extra protection against any Debug
Register access even in Real Mode or at privilege level 0 in Protected Mode. This
additional protection feature is provided to guarantee that a software debugger can
have full control over the Debug Register resources when required. The GD bit, when
set, causes an exception 1 fault when an instruction attempts to read or write any
Debug Register. The GD bit is automatically cleared when the exception 1 handler is
invoked, allowing the exception 1 handler free access to the debug registers.
GE and LE (Exact data breakpoint match, global and local)
The Intel
®
Quark SoC X1000 Core always does exact data breakpoint matching,
regardless of GE/LE bit settings. Any data breakpoint trap is reported exactly after
completion of the instruction that caused the operand transfer. Exact reporting is
provided by forcing the Intel
®
Quark SoC X1000 Core execution unit to wait for
completion of data operand transfers before beginning execution of the next
instruction.
When the Intel
®
Quark SoC X1000 Core performs a task switch, the LE bit is cleared.
Thus, the LE bit supports fast task switching out of tasks that have enabled the exact
data breakpoint match for their task-local breakpoints. The LE bit is cleared by the
Intel
®
Quark SoC X1000 Core during a task switch to avoid having exact data
breakpoint match enabled in the new task. Note that exact data breakpoint match must
be re-enabled under software control.
The Intel
®
Quark SoC X1000 Core GE bit is unaffected during a task switch. The GE bit
supports exact data breakpoint match that remains enabled during all tasks executing
in the system.
Note that instruction execution breakpoints are always reported exactly.