Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 255
Instruction Set Summary—Intel
®
Quark Core
12.2.3 Encoding of Integer Instruction Fields
Within the instruction are several fields that indicate register selection, addressing
mode and so on. The exact encodings of these fields are defined in this section.
12.2.3.1 Encoding of Operand Length (w) Field
For any given instruction that performs a data operation, the instruction executes as a
32-bit operation or a 16-bit operation. Within the constraints of the operation size, the
w field encodes the operand size as either one byte or the full operation size, as shown
in Table 76.
12.2.3.2 Encoding of the General Register (reg) Field
The general register is specified by the reg field, which may appear in the primary
opcode bytes, as the reg field of the “mod r/m” byte, or as the r/m field of the “mod
r/m” byte.
Table 76. Encoding of Operand Length (w) Field
w Field
Operand Size during 16-Bit Data
Operations
Operand Size during 32-Bit Data
Operations
0 8 Bits 8 Bits
1 16 Bits 32 Bits
Table 77. Encoding of reg Field when the (w) Field is Not Present in Instruction
reg Field
Register Selected during 16-Bit
Data Operations
Register Selected during 32-Bit
Data Operations
000 AX EAX
001 CX ECX
010 DX EDX
011 BX EBX
100 SP ESP
101 BP EBP
110 SI ESI
111 DI EDI