Specifications

Intel
®
Quark Core—Instruction Set Summary
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
256 Order Number: 329679-001US
12.2.3.3 Encoding of the Segment Register (sreg) Field
The sreg field in certain instructions is a 2-bit field allowing one of the four segment
registers to be specified. The sreg field in other instructions is a 3-bit field, allowing the
Intel
®
Quark SoC X1000 Core FS and GS segment registers to be specified.
Table 78. Encoding of reg Field when the (w) Field is Present in Instruction
Register Specified by reg Field during 16-Bit Data Operations:
reg
Function of w Field
(when w = 0) (when w = 1)
000 AL AX
001 CL CX
010 DL DX
011 BL BX
100 AH SP
101 CH BP
110 DH SI
111 BH DI
Register Specified by reg Field during 32-Bit Data Operations
reg
Function of w Field
(when w = 0) (when w = 1)
000 AL EAX
001 CL ECX
010 DL EDX
011 BL EBX
100 AH ESP
101 CH EBP
110 DH ESI
111 BH EDI
Table 79. 2-Bit sreg2 Field
2-bit sreg2 Field Segment Register Selected
00 ES
01 CS
10 SS
11 DS