Specifications

Intel
®
Quark Core—Instruction Set Summary
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
258 Order Number: 329679-001US
Table 81. Encoding of 16-Bit Address Mode with “mod r/m” Byte
mod r/m Effective Address mod r/m Effective Address
00 000 DS:[BX+SI] 10 000 DS:[BX+SI+d16]
00 001 DS:[BX+DI] 10 001 DS:[BX+DI+d16]
00 010 SS:[BP+SI] 10 010 SS:[BP+SI+d16]
00 011 SS:[BP+DI] 10 011 SS:[BP+DI+d16]
00 100 DS:[SI] 10 100 DS:[SI+d16]
00 101 DS:[DI] 10 101 DS:[DI+d16]
00 110 DS:d16 10 110 SS:[BP+d16]
00 111 DS:[BX] 10 111 DS:[BX+d16]
01 000 DS:[BX+SI+d8] 11 000 register–see below
01 001 DS:[BX+DI+d8] 11 001 register–see below
01 010 SS:[BP+SI+d8] 11 010 register–see below
01 011 SS:[BP+DI+d8] 11 011 register–see below
01 100 DS:[SI+d8] 11 100 register–see below
01 101 DS:[DI+d8] 11 101 register–see below
01 110 SS:[BP+d8] 11 110 register–see below
01 111 DS:[BX+d8] 11 111 register–see below
Register Specified by r/m during
16-Bit Data Operations
Register Specified by r/m during
32-Bit Data Operations
mod r/m
Function of w Field
mod r/m
Function of w Field
(when w=0) (when w =1) (when w=0) (when w =1)
11 000 AL AX 11 000 AL EAX
11 001 CL CX 11 001 CL ECX
11 010 DL DX 11 010 DL EDX
11 011 BL BX 11 011 BL EBX
11 100 AH SP 11 100 AH ESP
11 101 CH BP 11 101 CH EBP
11 110 DH SI 11 110 DH ESI
11 111 BH DI 11 111 BH EDI