Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 267
Instruction Set Summary—Intel
®
Quark Core
Table 89. Clock Count Summary (Sheet 1 of 13)
Instruction Format
Cache
Hit
Penalty
if
Cache
Miss
Notes
INTEGER OPERATIONS
MOV = Move:
reg1 to reg2 1000 100w : 11 reg1 reg2 1
reg2 to reg1 1000 101w : 11 reg1 reg2 1
memory to reg 1000 100w : mod reg r/m 1 2
Immediate to reg 1100 011w : 11000 reg : immediate data 1
or 1011W reg : immediate data 1
Immediate to Memory
1100 01w : mod 000 r/m : displacement
immediate
1
Memory to Accumulator 1010 000w : full displacement 1 2
Accumulator to Memory 1010 001w : full displacement 1
MOVSX/MOVZX = Move with Sign/Zero Extension
reg2 to reg1 0000 1111 : 1011 z11w : 11 reg1 reg2 3
memory to reg 0000 1111 : 1011 z11w : mod reg r/m 3 2
z instruction
0MOVZX
1MOVSX
PUSH = Push
reg 1111 1111 : 11 110 reg 4
or 01010 reg 1
memory 1111 1111 : mod 110 r/m 4 1 1
immediate 0110 10s0 : immediate data 1
PUSHA = Push All 0110 0000 11
POP = Pop
reg 1000 1111 : 11 000 reg 4 1
or 01011 reg 1 2
memory 1000 1111 : mod 000 r/m 5 2 1
POPA = Pop All 0110 0001 9 7/15 16/32
XCHG = Exchange
reg1 with reg2 1000 011w : 11 reg1 reg2 3 2
Accumulator with reg 10010 reg 3 2
Memory with reg 1000 011w : mod reg r/m 5 2
NOP = No Operation 1001 0000 1
Note: See Table 92 for notes and abbreviations for items in this table.