Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 271
Instruction Set Summary—Intel
®
Quark Core
CWD = Convert Word to
Dword
1001 1001 3
Instruction
ROL = Rotate Left
ROR = Rotate Right
RCL = Rotate Through Carry
Left
RDR = Rotate Through Carry
Right
SHL/SAL = Shift Logical/
Arithmetic Left
SHR = Shift Logical Right
SAR = Shift Arithmetic Right
TTT
000
001
010
011
100
101
111
Not Through Carry (ROL, ROR, SAR, SHL, and SHR)
reg by 1 1101 000w : 11 TTT reg 3
memory by 1 1101 000w : mod TTT r/m 4 6
reg by CL 1101 001w : 11 TTT reg 3
memory by CL 1101 001w : mod TTT r/m 4 6
reg by immediate count 1100 000w : 11 TTT reg : imm. 8-bit data 2
mem by immediate count
1100 000w : mod TTT r/m : imm. 8-bit
data
46
Through Carry (RCL and RCR)
reg by 1 1101 000w : 11 TTT reg 3
memory by 1 1101 000w : mod TTT r/m 4 6
reg by CL 1101 001w : 11 TTT reg 8/30 MN/MX,4
memory by CL 1101 001w : mod TTT r/m 9/31 MN/MX,5
reg by immediate count 1100 000w : 11 TTT reg : imm. 8-bit data 8/30 MN/MX,4
mem by immediate count
1100 000w : mod TTT r/m : imm. 8-bit
data
9/31 MN/MX,5
Instruction
SHLD = Shift Left Double
SHRD = Shift Right Double
TTT
100
101
register with immediate
0000 1111 : 10TT T100 : 11 reg2 reg1
: imm. 8-bit data
2
memory with immediate
0000 1111 : 10TT T100 : mod reg r/m
: imm. 8-bit data
36
register by CL 0000 1111 : 10TT T101 : 11 reg2 reg1 3
memory by CL 0000 1111 : 10TT T101 : mod reg r/m 4 5
BSWAP = Byte Swap 0000 1111 : 11001 reg 1
XADD = Exchange and Add
reg1, reg2 0000 1111 : 1100 000w : 11 reg2 reg1 3
memory, reg 0000 1111 : 1100 000w : mod reg r/m 4 6/2 U/L
CMPXCHG = Compare and Exchange
reg1, reg2 0000 1111 : 1011 000w : 11 reg2 reg1 6
memory, reg 0000 1111 : 1011 000w : mod reg r/m 7/10 2 6
Table 89. Clock Count Summary (Sheet 5 of 13)
Instruction Format
Cache
Hit
Penalty
if
Cache
Miss
Notes
Note: See Table 92 for notes and abbreviations for items in this table.