Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 273
Instruction Set Summary—Intel
®
Quark Core
RET = Return from CALL (within segment)
1100 0011 5 5
Adding Immediate to SP 1100 0010 : 16-bit disp. 5 5
ENTER = Enter Procedure 1100 1000 : 16-bit disp., 8-bit level
Level = 0
Level = 1
Level (L) > 1
14
17
17+3L 8
LEAVE = Leave Procedure 1100 1001 5 1
MULTIPLE-SEGMENT INSTRUCTIONS
MOV = Move
reg. to segment reg. 1000 1110 : 11 sreg3 reg 3/9 0/3 RV/P,9
memory to segment reg. 1000 1110 : mod sreg3 r/m 3/9 2/5 RV/P,9
segment reg. to reg. 1000 1100 : 11 sreg3 reg 3
segment reg. to memory 1000 1100 : mod sreg3 r/m 3
PUSH = Push
segment reg.
(ES, CS, SS, or DS)
000sreg 2110 3
segment reg. (FS or GS) 0000 1111 : 10 sreg3001 3
POP = Pop
segment reg.
(ES, CS, SS, or DS)
000sreg 2111 3/0 2/5 RV/P,9
segment reg. (FS or GS) 0000 1111 : 10 sreg3001 3/9 2/5 RV/P,9
LDS = Load Pointer to DS 1100 0101 : mod reg r/m 6/12 7/10 RV/P,9
LES = Load Pointer to ES 1100 0100 : mod reg r/m 6/12 7/10 RV/P,9
LFS = Load Pointer to FS 0000 1111 : 1011 0100 : mod reg r/m 6/12 7/10 RV/P,9
LGS = Load Pointer to GS 0000 1111 : 1011 0101 : mod reg r/m 6/12 7/10 RV/P,9
LSS = Load Pointer to SS 0000 1111 : 1011 0010 : mod reg r/m 6/12 7/10 RV/P,9
CALL = Call
Direct intersegment 1001 1010 : unsigned full offset, selector 18 2 R,7,22
to same level
thru Gate to same level
to inner level, no parameters
to inner level, x parameters (d) words
to TSS
thru Task Gate
20
35
69
77+4X
37+TS
38+TS
3
6
17
17+n
3
3
P,9
P,9
P,9
P,11,9
P,10,9
P,10,9,
Indirect intersegment 1111 1111 : mod 011 r/m 17 8 R,7
to same level
thru Gate to same level
to inner level, no parameters
to inner level, x parameters (d) words
to TSS
thru Task Gate
20
35
69
77+4X
37+TS
38+TS
10
13
24
24+n
10
10
P,9
P,9
P,9
P,11,9
P,10,9
P,10,9,
Table 89. Clock Count Summary (Sheet 7 of 13)
Instruction Format
Cache
Hit
Penalty
if
Cache
Miss
Notes
Note: See Table 92 for notes and abbreviations for items in this table.