Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 277
Instruction Set Summary—Intel
®
Quark Core
INVD = Invalidate Data
Cache
0000 1111 : 0000 1000 4
WBINVD = Write-Back and
Invalidate Data Cache
0000 1111 : 0000 1001 5
INVLPG = Invalidate TLB Entry
INVLPG memory 0000 1111 : 0000 0001 : mod 111 r/m 12/11 H/NH
PREFIX BYTES
Address Size Prefix 0110 0111 1
LOCK = Bus Lock Prefix 1111 0000 1
Operand Size Prefix 0110 0110 1
Segment Override Prefix
CS: 0010 1110 1
DS: 0011 1110 1
ES: 0010 0110 1
FS: 0110 0100 1
GS: 0110 0101 1
SS: 0011 0110 1
PROTECTION CONTROL
ARPL = Adjust Requested Privilege Level
From register 0110 0011 : 11 reg1 reg2 9
From memory 0110 0011 : mod reg r/m 9
LAR = Load Access Rights
From register 0000 1111 : 0000 0010 : 11 reg1 reg2 11 3
From memory 0000 1111 : 0000 0010 : mod reg r/m 11 5
LGDT = Load Global Descriptor
Table register 0000 1111 : 0000 0001 : mod 010 r/m 12 5
LIDT = Load Interrupt Descriptor
Table register 0000 1111 : 0000 0001 : mod 011 r/m 12 5
LLDT = Load Local Descriptor
Table register from reg. 0000 1111 : 0000 0000 : 11 010 reg 11 3
Table register from mem. 0000 1111 : 0000 0000 : mod 010 r/m 11 6
LMSW = Load Machine Status Word
From register 0000 1111 : 0000 0001 : 11 110 reg 13
From memory 0000 1111 : 0000 0001 : mod 110 r/m 13 1
LSL = Load Segment Limit
From register 0000 1111 : 0000 0011 : 11 reg1 reg2 10 3
From memory 0000 1111 : 0000 0011 : mod reg r/m 10 6
Table 89. Clock Count Summary (Sheet 11 of 13)
Instruction Format
Cache
Hit
Penalty
if
Cache
Miss
Notes
Note: See Table 92 for notes and abbreviations for items in this table.