Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 295
Signal Descriptions—Intel
®
Quark Core
WRITE-BACK ENHANCED Intel
®
Quark Core SIGNAL PINS
CACHE# O
The CACHE# output indicates internal cacheability on read cycles and burst write-back on write cycles.
CACHE# is asserted for cacheable reads, cacheable code fetches and write-backs. It is driven inactive for
non-cacheable reads, I/O cycles, special cycles, and write-through cycles.
FLUSH# I
Cache Flush# is an existing pin that operates differently when the processor is configured as Enhanced
Bus mode (write-back). FLUSH# causes the processor to write back all modified lines and flush
(invalidate) the cache. FLUSH# is asynchronous, but must meet setup and hold times t20 and t21 for
recognition in any specific clock.
HITM# O
The Hit/Miss to a Modified Line pin is a cache coherency protocol pin that is driven only in Enhanced
Bus mode. When a snoop cycle is run, HITM# indicates that the processor contains the snooped line and
that the line has been modified. Assertion of HITM# implies that the line is written back in its entirety,
unless the processor is already in the process of doing a replacement write-back of the same line.
INV I
The Invalidation Request pin is a cache coherency protocol pin that is used only in Enhanced Bus
mode. It is sampled by the processor on EADS#-driven snoop cycles. It is necessary to assert this pin to
get the effect of the processor invalidate cycle on write-through-only lines. INV also invalidates the write-
back lines. However, when the snooped line is modified, the line is written back and then invalidated. INV
must satisfy setup and hold times t12 and t13 for proper operation.
PLOCK# O
In the Enhanced bus mode, Pseudo-Lock Output is always driven inactive. In this mode, a 64-bit data
read (caused by an FP operand access or a segment descriptor read) is treated as a multiple cycle read
request, which may be a burst or a non-burst access based on whether BRDY# or RDY# is asserted by
the system. Because only write-back cycles (caused by Snoop write-back or replacement write-back) are
write burstable, a 64-bit write is driven out as two non-burst bus cycles. BLAST# is asserted during both
writes. Refer to the Bus Functional Description section 10.3 for details on Pseudo-Locked bus cycles.
SRESET I
For the Write-Back Enhanced Intel
®
Quark Cores, Soft Reset operates similar to other Intel
®
Quark
Cores. On SRESET, the internal SMRAM base register retains its previous value, does not flush, write-back
or disable the internal cache. Because SRESET is treated as an interrupt, it is possible to have a bus cycle
while SRESET is asserted. SRESET is serviced only on an instruction boundary. SRESET is asynchronous
but must meet setup and hold times t20 and t21 for recognition in any specific clock.
WB/WT# I
The Write-Back/Write-Through pin enables Enhanced Bus mode (write-back cache). It also defines a
cached line as write-through or write-back. For cache configuration, WB/WT# must be valid during RESET
and be active for at least two clocks before and two clocks after RESET is deasserted. To define write-back
or write-through configuration of a line, WB/WT# is sampled in the same clock as the first RDY# or
BRDY# is asserted during a line fill (allocation) cycle.
Table 95. Intel
®
Quark SoC X1000 Core Pin Descriptions (Sheet 5 of 5)
Symbol Type Name and Function