Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 299
Testability—Intel
®
Quark Core
will be corrupted. This is because the testability operations use hardware that is used in
normal memory accesses for the Intel
®
Quark SoC X1000 Core whether the cache is
enabled or not.
B.1.4 Flush Cache
The control bits in TR5 must be written with 11 to flush the cache. None of the other
bits in TR5 have any meaning when 11 is written to the control bits. Flushing the cache
resets the LRU bits and the valid bits to 0, but does not change the cache tag or data
arrays.
When the cache is flushed by writing to TR5 the special bus cycle indicating a cache
flush to the external system is not run (see Section 10.3.11). For normal operation, the
cache should be flushed with the instruction INVD (Invalidate Data Cache) instruction
or the WBINVD (Write-back and Invalidate Data Cache) instruction.
B.1.5 Additional Cache Testing Features for Write-Back Enhanced
Intel
®
Quark SoC X1000 Core
When in Enhanced Bus (Write-Back) mode, the Write-Back Enhanced Intel
®
Quark SoC
X1000 Core cache testing is a superset of the Standard Bus (Write-Through) mode. The
additional cache testing features are summarized below.
There are two state bits per cache line (VH and VL) instead of one (V). The assignment
of VH and VL state bits is shown in Table 97.
The state assignments have been chosen so that VH is identical to the V-state of the
Intel
®
Quark SoC X1000 Core, when the Write-Back Enhanced Intel
®
Quark SoC X1000
Core is in Standard Bus mode and where only S and I states are possible.
There are no changes to TR3 between the Standard Bus mode and the Enhanced Bus
mode. The TR4 definition remains the same in Standard Bus mode. The changes to TR4
in Enhanced Bus mode are shown in Figure 130.
In Enhanced Bus mode, the cache line state bits of all four lines of the set are no longer
available, which eliminates the possibility of a conflicting definition of state bits for the
selected entry. The entry's state bits are moved to positions 0 and 1.
TR5 is also the same in Standard Bus mode. A minor change to TR5 in Enhanced Bus
mode is illustrated in Figure 131.
In Enhanced Bus mode, control bit TR5.SLF (bit 13) is added to allow 1,1 of TR5.CTL
(bits 1:0) to perform two different kinds of cache flushes. When SLF=0, CTL=1,1
performs a single clock invalidate of all lines in the cache, which does not write-back
M-state lines. When SLF=1, the specific line addressed is written back (IF in M-State)
and invalidated. The state of SLF is significant only when CTL=1,1.
Table 97. State Bit Assignments for the Write-Back Enhanced Intel
®
Quark SoC X1000
Core
State VH, VL
M1, 1
E0, 1
S1, 0
I0, 0