Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 301
Testability—Intel
®
Quark Core
B.2.2 TLB Test Registers TR6 and TR7
The two TLB test registers are shown in Figure 133. TR6 is the command test register
and TR7 is the data test register. External access to these registers is provided through
MOV reg,TREG and MOV TREG,reg instructions.
B.2.2.1 Command Test Register: TR6
TR6 contains the tag information and control information used in a TLB test. Loading
TR6 with tag and control information initiates a TLB write or lookup test.
TR6 contains three bit fields, a 20-bit linear address (bits 31:12), seven bits for the TLB
tag protection bits (bits 11:5) and one bit (bit 0) to define the type of operation to be
performed on the TLB.
The 20-bit linear address forms the tag information used in the TLB access. The lower
three bits of the linear address select which of the eight sets are accessed. The upper
17 bits of the linear address form the tag stored in the tag array.
Figure 132. TLB Organization