Specifications

Intel
®
Quark Core—Testability
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
304 Order Number: 329679-001US
TR6 must be written to initiate the TLB write operation. Bit 0 in TR6 must be reset to
zero to indicate a TLB write. The 20-bit linear address and the seven page protection
bits must also be written in TR6 to specify the tag portion of the TLB entry. Note that
the three least significant bits of the linear address specify which of the eight sets in
the data block is loaded with the physical address data. Thus only 17 of the linear
address bits are stored in the tag array.
B.2.4 TLB Lookup Test
To perform a TLB lookup it is only necessary to write the proper tags and control
information into TR6. Bit 0 in TR6 must be set to 1 to indicate a TLB lookup. TR6 must
be loaded with a 20-bit linear address and the seven protection bits. To force misses
and matches of the individual protection bits on TLB lookups, set the seven protection
bits as specified in Table 98.
A TLB lookup operation is initiated by the write to TR6. TR7 indicates the result of the
lookup operation following the write to TR6. The hit/miss indication can be found in TR7
bit 4 (see Table 101).
TR7 contains the following information if bit 4 indicates that the lookup test resulted in
a hit.
Bits 3:2 specify the set in which the match occurred. The 22 most significant bits in TR7
contain the physical address and page attributes contained in the entry. Bits 9:7
contain the LRU bits associated with the accessed set. The state of the LRU bits is does
not reflect their being updated for the current lookup.
When bit 4 in TR7 indicates that the lookup test resulted in a miss, the remaining bits in
TR7 are undefined.
Again it should be noted that a TLB testability lookup operation affects the state of the
LRU bits. The LRU bits are updated if a hit occurs. The entry which was hit becomes the
most recently used.
B.3 Intel
®
Quark SoC X1000 Core JTAG
The Intel
®
Quark SoC X1000 Core provides additional testability features compatible
with the IEEE Standard Test Access Port.
B.3.1 Test Access Port (TAP) Controller
The TAP controller is a synchronous, finite state machine. It controls the sequence of
operations of the test logic. The TAP controller changes state only in response to the
following events:
1. A rising edge of TCK
2. Power-up
The value of the test mode state (TMS) input signal at a rising edge of TCK controls the
sequence of the state changes. The state diagram for the TAP controller is shown in
Figure 134. Test designers must consider the operation of the state machine in order to
design the correct sequence of values to drive on TMS.