Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 33
Architectural Overview—Intel
®
Quark Core
3.6.2 Little Endian vs. Big Endian Data Formats
The Intel
®
Quark SoC X1000 Core, as well as all other members of the Intel
architecture, use the “little-endian” method for storing data types that are larger than
one byte. Words are stored in two consecutive bytes in memory with the low-order byte
at the lowest address and the high order byte at the high address. Dwords are stored in
four consecutive bytes in memory with the low-order byte at the lowest address and
the high order byte at the highest address. The address of a word or dword data item is
the byte address of the low-order byte.
Figure 8 illustrates the differences between the big-endian and little-endian formats for
dwords. The 32 bits of data are shown with the low order bit numbered bit 0 and the
high order bit numbered 32. Big-endian data is stored with the high-order bits at the
lowest addressed byte. Little-endian data is stored with the high-order bits in the
highest addressed byte.
The Intel
®
Quark SoC X1000 Core has the following two instructions that can convert
16- or 32-bit data between the two byte orderings:
• BSWAP (byte swap) handles 4-byte values
• XCHG (exchange) handles 2-byte values
Figure 8. Big vs. Little Endian Memory Format
3.7 Interrupts
3.7.1 Interrupts and Exceptions
Interrupts and exceptions alter the normal program flow, in order to handle external
events, to report errors or exceptional conditions. The difference between interrupts
and exceptions is that interrupts are used to handle asynchronous external events
while exceptions handle instruction faults. Although a program can generate a software
interrupt via an INT N instruction, the Intel
®
Quark SoC X1000 Core treats software
interrupts as exceptions.
Hardware interrupts occur as the result of an external event and are classified into two
types: maskable or non-maskable. Interrupts are serviced after the execution of the
current instruction. After the interrupt handler is finished servicing the interrupt,
execution proceeds with the instruction immediately after the interrupted instruction.
Section 3.7.3 and Section 3.7.4 discuss the differences between Maskable and Non-
Maskable interrupts.
A5163-01
0
87
Dword in Little-Endian Memory Format
16 1524 2331
m + 3
m + 2
m + 1
m
0
87
Dword in Big-Endian Memory Format
16 1524 2331
m
m + 1
m + 2
m + 3