Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 37
Architectural Overview—Intel
®
Quark Core
As the Intel
®
Quark SoC X1000 Core executes instructions, it follows a consistent cycle
in checking for exceptions. Consider the case of the Intel
®
Quark SoC X1000 Core
having just completed an instruction. It then performs the checks listed in Table 7
before reaching the point where the next instruction is completed. This cycle is
repeated as each instruction is executed, and occurs in parallel with instruction
decoding and execution. Checking for EM, TS, or FPU error status only occurs for
processors with on-chip Floating-Point Units.
3.7.7 Instruction Restart
The Intel
®
Quark SoC X1000 Core fully supports restarting all instructions after faults.
If an exception is detected in the instruction to be executed (exception categories 4
through 10 in Table 8), the Intel
®
Quark SoC X1000 Core invokes the appropriate
exception service routine.
The Intel
®
Quark SoC X1000 Core is in a state that permits restart of the instruction,
for all cases except the following. An instruction causes a task switch to a task whose
Task State Segment is partially “not present.” (An entirely “not present” TSS is
restartable.) Partially present TSSs can be avoided either by keeping the TSSs of such
tasks present in memory, or by aligning TSS segments to reside entirely within a single
4 K page (for TSS segments of 4 Kbytes or less).
Note: Partially present task state segments can be easily avoided by proper design of the
operating system.
Table 7. Sequence of Exception Checking
Sequence Description
1
Check for Exception 1 Traps from the instruction just completed (single-step via Trap Flag, or
Data Breakpoints set in the Debug Registers).
2
Check for Exception 1 Faults in the next instruction (Instruction Execution Breakpoint set in
the Debug Registers for the next instruction).
3 Check for external NMI and INTR.
4
Check for Segmentation Faults that prevented fetching the entire next instruction
(exceptions 11 or 13).
5 Check for Page Faults that prevented fetching the entire next instruction (exception 14).
6
Check for Faults decoding the next instruction (exception 6 if illegal opcode; exception 6 if in
Real Mode or in Virtual 8086 Mode and attempting to execute an instruction for Protected
Mode only (see Section 6.5.4, “Protection and I/O Permission Bitmap” on page 109); or
exception 13 if instruction is longer than 15 bytes, or privilege violation in Protected Mode
(i.e., not at IOPL or at CPL=0).
7 If WAIT opcode, check if TS=1 and MP=1 (exception 7 if both are 1).
8 If opcode for Floating-Point Unit, check if EM=1 or TS=1 (exception 7 if either are 1).
9
If opcode for Floating-Point Unit (FPU), check FPU error status (exception 16 if error status is
asserted).
10
Check in the following order for each memory reference required by the instruction:
a. Check for Segmentation Faults that prevent transferring the entire memory quantity
(exceptions 11, 12, 13).
b. Check for Page Faults that prevent transferring the entire memory quantity (exception
14).
Note: The order stated supports the concept of the paging mechanism being “underneath” the
segmentation mechanism. Therefore, for any given code or data reference in memory,
segmentation exceptions are generated before paging exceptions are generated.